First determine whether the failed item is emissions or immunity, then judge whether it is a single-point exceedance or a full-band rise. Single-point exceedances are mostly resonance and routing problems, while full-band rises are mostly grounding, shielding, or filtering design defects. Locate the problem clearly before touching the hardware, to avoid blindly adding components.
When accepting EMC projects, the company's laboratory first issues pre-test scan data, marking the exceeding frequencies, margins, and test setup conditions, on which basis companies decide the direction of remediation. The database currently holds 347 testing laboratories and 40,930 product records, which can serve as comparison references for similar products.
First, radiated emissions (RE) exceedance. Commonly seen in switching power supplies, clock circuits, and high-speed interfaces, manifesting as exceedances at specific frequencies or harmonic families. Remediation measures include adjusting the switching frequency, adding common-mode inductors, optimizing PCB return paths, and adding shielding cans.
Second, conducted emissions (CE) exceedance. Concentrated in the low-frequency band of power ports. Remediation measures are adding common-mode inductors and X/Y capacitors, improving grounding, and replacing with low-noise switching devices.
Third, electrostatic discharge (ESD) immunity failure. Mostly caused by insufficient discharge paths at enclosure gaps, buttons, and interfaces. Remediation measures are adding TVS diodes, adjusting discharge gaps, and adding insulating sheets and grounding springs.
Fourth, electrical fast transient (EFT) failure. Commonly seen at power and signal ports, mostly due to insufficient filtering and isolation. Remediation measures are adding common-mode inductors and ferrite beads, and improving ground plane continuity.
Fifth, surge failure. Mostly occurs when protection devices at the power inlet are undersized or the layout is too long. Remediation measures are replacing varistors and gas discharge tubes, and shortening the discharge path.
Sixth, radiated immunity (RS) failure. Manifests as functional abnormalities in specific frequency bands. Remediation measures are adding shielding, adding decoupling, and optimizing cable shield termination.
Seventh, harmonic current and voltage flicker failure. Mostly related to the design of the power factor correction circuit. Remediation measures are adding a PFC circuit and adjusting filter parameters.
Structural problems are cheap to fix; device selection problems are expensive. Routing, grounding, and shielding remediation usually involves only PCB revisions and minor structural adjustments; wrong power topology and protection device selection may trigger re-tooling and re-certification.
| Failure Type | Typical Remediation Measures | PCB Change Required | Structural Part Re-tooling Required | Timeline Range |
|---|---|---|---|---|
| Radiated emissions RE | Common-mode inductors, shielding cans, clock optimization | Mostly yes | Rarely yes | 1-3 weeks |
| Conducted emissions CE | Common-mode inductors, X/Y capacitors, grounding improvement | Mostly yes | No | 1-2 weeks |
| Electrostatic discharge ESD | TVS diodes, discharge gaps, grounding springs | Rarely yes | Partly yes | 1-2 weeks |
| Electrical fast transient EFT | Ferrite beads, common-mode inductors, ground plane optimization | Rarely yes | No | 1-2 weeks |
| Surge | Varistors, gas discharge tubes, path shortening | Mostly yes | No | 1-2 weeks |
| Radiated immunity RS | Shielding, decoupling, cable termination | Rarely yes | Partly yes | 1-3 weeks |
| Harmonic current | PFC circuit, filter parameter adjustment | Yes | No | 2-4 weeks |
The cost range depends on whether tooling changes and full-item retesting are required. Tooling change costs are usually higher than the electrical remediation itself, so structural-part-related ESD and RS problems should be prioritized for resolution at the design stage.
The core value of pre-testing is reducing repeat rounds of formal testing and the probability of tooling changes. Each round of formal testing incurs site and labor costs, and if the first round fails, the second round often requires re-queuing. Pre-testing exposes exceeding frequencies in advance under in-house setup conditions, completing remediation before tooling is opened.
According to the process, pre-testing can complete one full-item scan before formal testing; formal testing is usually scheduled for 1 round, with retests added according to failed items. The SDoC cycle is 1-2 weeks. In the past 30 days, 1,156 new certificates were issued and 695 new companies were added; the database holds 26,862 companies in total, of which 16,734 are Chinese companies, with 6,103 FCC certificates, indicating that a large number of comparable samples exist for the compliance paths of similar products, and at the pre-testing stage same-category data can be used to judge whether margins are sufficient.
First, define the grounding architecture first. Ground plane continuity and single-point versus multi-point grounding are determined at the schematic stage; later changes are the most costly.
Second, reserve device positions at the power inlet according to protection level. The positions and trace lengths of varistors, common-mode inductors, and X/Y capacitors are locked in at the layout stage.
Third, apply ground guarding to high-speed clocks and interfaces. Reserve shielding and grounding pads for clock lines, differential pairs, and connector areas.
Fourth, reserve shielding and discharge paths in structural parts. Reserve positions for springs, conductive foam, and TVS at enclosure gaps, buttons, and interface openings.
Fifth, complete one round of pre-testing at the prototype stage. Complete the scan before tooling and mass production, keeping the remediation window within the design stage.
First obtain the exceeding frequencies and test setup records, judge whether it is a single-point exceedance or a full-band rise, and then decide whether to change the circuit or the structure.
Not necessarily. ESD, EFT, and some RS problems can be solved through structural parts, cables, and termination methods; only conducted and radiated emissions mostly require board changes.
Pre-testing is used to expose exceeding frequencies and items with insufficient margin in advance, while formal testing issues the compliance conclusion. Pre-testing cannot replace formal testing.
Electrical remediation mostly takes 1-2 weeks, and 2-4 weeks when tooling changes and full-item retesting are involved. The SDoC cycle is 1-2 weeks.
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Email Mr. TaoBeice Testing · Tao Gong · CNAS L5516 · CMA 202319013572 · NTEK Group Partner Lab · Shenzhen, China
+86 199-2684-3993 · taowushuang@ntek.org.cn · 中文站